View MM908E626AVDWBR2_2097876.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

vss evss vssa vrefl vdd evdd vdda vrefh lin fgen ptd1/tach1 pte1/rxd rxd ptd0/tach0/bemf ptb1/ad1 bemf ss irq_a rst_a irq rst port c i/os port b i/os port a i/os hvdd hb4 hb3 hb2 hb1 ep gnd[1:2] vsup[1:3] 908e626 908e626 simplified application diagram switchable internal v dd output microcontroller ports bipolar step motor n s motorola semiconductor technical data this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 2004 document order number: mm908e626 rev 1.0, 11/2004 908e626 advance information stepper motor driver with embedded mcu and lin integrated stepper motor driver with embedded mcu and lin serial communication the 908e626 is an integrated single-pa ckage solution that includes a high- performance hc08 microcontroller with a smartmos tm analog control ic. the hc08 includes flash memory, a timer, enhanced serial communications interface (esci), an analog-to-digital converter (adc), serial peripheral interface (spi) (only internal), and an internal clock generator (icg) module. the analog control die provides fully protected h-bridge outputs, voltage regulator, autonomous watchdog, and local interconnect network (lin) physical layer. the single-package solution, together with lin, provides optimal application performance adjustments and sp ace-saving pcb design. it is well suited for the control of automotive st epper applications like climate control and light-levelling. features ? high-performance m68hc08ey16 core ? 16 k bytes of on-chip flash memory ? 512 bytes of ram ? internal clock generation module ? two 16-bit, 2-channel timers ? 10-bit analog-to-digital converter ? four low r ds(on) half-bridge outputs ? 13 microcontroller i/os dwb suffix case 1400-01 54-terminal soicwb-ep ordering information device temperature range (t a ) package mm908e626avdwb/r2 -40c to 115c 54 soic wb-ep 908e626 simplified application diagram note applications with multiple stepper motors in one system (e.g., climate control) typically have a central reverse battery protection. 908e626 simplified application diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 2 figure 1. 908e626 simplified internal block diagram figure 1. 908e626 simplified internal block diagram control and status register, 64 bytes user flash, 15,872 bytes user ram, 512 bytes monitor rom, 310 bytes user flash vector space, 36 bytes flash programming (burn in) rom, 1024 bytes 5-bit keyboard interrupt module 2-channel timer interface module a security module 2-channel timer interface module b m68hc08 cpu cpu registers alu periodic wake-up timebase module arbiter module serial pheripheral interface module prescaler module internal clock generator module computer operating properly module single breakpoint break module power-on reset module 24 internal system integration module 10 bit analog-to- digital converter module enhanced serial communication interface module irq ptb6/ad6/tbch0 rst vrefl vssa evss evdd vdda vrefh ptb7/ad7/tbch1 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb0/ad0 pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 ptc4/osc1 ptc3/osc2 ptc2/mclk flsvpp pta5/spsck ptc1/mosi ptc0/miso pte0/txd ptd1/tach1 single external irq module configuration register module bemf module port a ddra osc2 osc1 rst power irq vrefh vdda vrefl vssa vdd vss port b ddrb pta6/ss pta5/spsck pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb2/ad2 ptb1/ad1 ptb0/ad0 port c port d ddrc ddrd ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso ddre port e ptd1/tach1 ptd0/tach0 pte1/rxd pte0/txd internal bus ptd0/tach0 ptb1/ad1 pte1/rxd voltage regulator spi & control reset control module autonomous watchdog lin physical layer analog multiplexer half bridge driver & diagnostic switched vdd driver & diagnostic vss vdd hvdd hb1 hb2 hb3 hb4 irq_a rst_a ss bemf fgen vsup1-3 gnd1-2 lin adout txd spsck mosi miso rxd chip temp vsup prescaler interrupt control module vsup vsup vsup vsup fgen bemf ss half bridge driver & diagnostic fgen bemf half bridge driver & diagnostic fgen bemf half bridge driver & diagnostic fgen bemf analog die mcu die f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 3 pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 vrefh vdda evdd evss vssa vrefl pte1/rxd rxd vss nc vdd nc nc nc hvdd nc hb4 vsup3 gnd2 hb3 nc flsvpp ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptc4/osc1 ptc3/osc2 ptc2/mclk ptb5/ad5 ptb4/ad4 ptb3/ad3 irq rst ptb1/ad1 ptd0/tach0/bemf ptd1/tach1 nc fgen bemf rst_a irq_a ss lin nc nc hb1 vsup1 gnd1 hb2 vsup2 1 11 12 13 14 15 16 17 18 19 20 9 10 21 22 23 24 25 26 27 6 7 8 4 5 2 3 54 44 43 42 41 40 39 38 37 36 35 46 45 34 33 32 31 30 29 28 49 48 47 51 50 53 52 exposed pad transparent top view of package terminal definitions a functional description of each terminal can be found in the system/application information section beginning on page 14 . die terminal terminal name formal name definition mcu 1 2 6 7 8 11 ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb1/ad1 port b i/os these terminals are special-functi on, bidirectional i/o port terminals that are shared with other functional modules in the mcu. mcu 3 4 5 ptc4/osc1 ptc3/osc2 ptc2/mclk port c i/os these terminals are special-functi on, bidirectional i/o port terminals that are shared with other functional modules in the mcu. mcu 9 irq external interrupt input this terminal is an asynchronous external interrupt input terminal. mcu 10 rst external reset this terminal is bidirectional, allowi ng a reset of the entire system. it is driven low when any internal reset source is asserted. mcu 12 13 ptd0/tach0/bemf ptd1/tach1 port d i/os these terminals are special-functi on, bidirectional i/o port terminals that are shared with other functional modules in the mcu. ? 14, 21, 22, 28, 33, 35, 36, 37, 39 nc no connect not connected. mcu 42 pte1/rxd port e i/o this terminal is a special- function, bidirectional i/o port terminal that can is shared with other functional modules in the mcu. mcu 43 48 vrefl vrefh adc references these terminals are the refe rence voltage terminals for the analog-to- digital converter (adc). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 4 mcu 44 47 vssa vdda adc supply terminals these terminals are the power supply terminals for the analog-to-digital converter. mcu 45 46 evss evdd mcu power supply terminals these terminals are the ground and po wer supply terminal s, respectively. the mcu operates from a single power supply. mcu 49 50 52 53 54 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 port a i/os these terminals are special-func tion, bidirectional i/o port terminals that are shared with other functional modules in the mcu. mcu 51 flsvpp test terminal for test purposes only. do not connect in the application. analog 15 fgen current limitation frequency input this is the input terminal for t he half-bridge current limitation pwm frequency. analog 16 bemf back electromagnetic force output this terminal gives the user info rmation about back el ectromagnetic force (bemf). analog 17 rst_a internal reset this terminal is the bidirectional reset terminal of the analog die. analog 18 irq_a internal interrupt output this terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. analog 19 ss slave select this terminal is the spi sl ave select terminal for the analog chip. analog 20 lin lin bus this terminal represents the single-wire bus transmitter and receiver. analog 23 26 29 32 hb1 hb2 hb3 hb4 half-bridge outputs this device includes power mosfets configured as four half-bridge driver outputs. these outputs may be configured for step motor drivers, dc motor drivers, or as hi gh-side and low-side switches. analog 24 27 31 vsup1 vsup2 vsup3 power supply terminals these terminals are devic e power supply terminals. analog 25 30 gnd1 gnd2 power ground terminals these terminals are devic e power ground connections. analog 34 hvdd switchable v dd output this terminal is a switchable v dd output for driving resistive loads requiring a regulated 5.0 v supply; e.g., 3-terminal hall-effect sensors. analog 38 vdd voltage regulator output the +5.0 v voltage regulator output terminal is intended to supply the embedded microcontroller. analog 40 vss voltage regulator ground ground terminal for the connection of all non-power ground connections (microcontroller and sensors). analog 41 rxd lin transceiver output this terminal is the output of lin transceiver. ? ep exposed pad exposed pad the exposed pad terminal on the bottom side of the package conducts heat from the chip to the pcb board. terminal definitions (continued) a functional description of each terminal can be found in the system/application information section beginning on page 14 . die terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 5 maximum ratings all voltages are with respect to ground unle ss otherwise noted. exceed ing limits on any terminal may cause permanent damage to the device. rating symbol value unit electrical ratings supply voltage analog chip supply voltage under no rmal operation (steady-state) analog chip supply voltage under transient conditions (note 1) microcontroller chip supply voltage v sup( ss ) v sup( pk ) v dd -0.3 to 28 -0.3 to 40 -0.3 to 6.0 v input terminal voltage analog chip microcontroller chip v in (analog) v in (mcu) -0.3 to 5.5 v ss -0.3 to v dd +0.3 v maximum microcontroller current per terminal all terminals except vdd, vss, pta0:pta6, ptc0:ptc1 terminals pta0:pta6, ptc0:ptc1 i pin (1) i pin (2) 15 25 ma maximum microcontroller v ss output current i mvss 100 ma maximum microcontroller v dd input current i mvdd 100 ma lin supply voltage normal operation (steady-state) transient conditions (note 1) v bus(ss) v bus(dynamic) -18 to 28 40 v esd voltage human body model (note 2) machine model (note 3) charge device model (note 4) v esd1 v esd2 v esd3 3000 150 500 v thermal ratings storage temperature t stg -40 to 150 c operating case temperature (note 5) t c -40 to 115 c operating junction temperature analog mcu (note 6) t j(analog) t j(mcu) -40 to 150 -40 to 135 c peak package reflow temperature during solder mounting (note 7) t solder 245 c thermal resistance (junction to ambient) all outputs on (note 8) , (note 10) single output on (note 9) , (note 10) r ja1 r ja2 24 27 c/w notes 1. transient capability for pulses with a time of t < 0.5 sec. 2. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 3. esd2 testing is performed in ac cordance with the machine model (c zap =200 pf, r zap =0 ? ). 4. esd3 testing is performed in accordanc e with charge device model, robotic (c zap =4.0 pf). 5. the limiting factor is junction temperat ure, taking into account the power dissipat ion, thermal resistance, and heat sinking. 6. in the 125c to 135c temperature range, the flash is guaranteed as read only. 7. terminal soldering temperature is for 10 seconds maximum durat ion. not designed for immersion soldering. exceeding these limi ts may cause malfunction or permanent damage to the device. 8. all outputs on and dissipating equal power. 9. one output on and dissipating power. 10. per jedec jesd51-2 at natural convection, still air condition; and 2s2p thermal te st board per jedec jesd51-7 and jesd51-5 ( thermal vias connected to top ground plane). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 6 static electrical characteristics all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 135 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit supply voltage nominal operating voltage v sup 8.0 ? 18 v supply current normal mode v sup = 12 v, power die on (pson=1), mcu operating using internal oscillator at 32 mhz (8.0 mhz bus frequency), spi, esci, adc enabled i run ?20? ma digital interface ra tings (analog die) output terminals rst_a , irq_a low-state output voltage (i out = -1.5 ma) high-state output voltage (i out = 1.0 a) v ol v oh ? 3.85 ? ? 0.4 ? v output terminals bemf, rxd low-state output voltage (i out = -1.5 ma) high-state output voltage (i out = 1.5 ma) v ol v oh ? 3.85 ? ? 0.4 ? v output terminal rxd?capacitance (note 11) c in ?4.0?pf input terminals rst_a , fgen, ss input logic low voltage input logic high voltage v il v ih ? 3.5 ? ? 1.5 ? v input terminals rst_a , fgen, ss ?capacitance (note 11) c in ?4.0?pf terminals rst_a , irq_a ?pullup resistor r pullup 1 ?10?k ? terminal ss ?pullup resistor r pullup 2 ?60?k ? terminals fgen, mosi, spsck?pulldown resistor r pulldown ?60?k ? terminal txd?pullup current source i pullup ?35? a notes 11. this parameter is guaranteed by process monitoring but is not production tested. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 7 system resets and interrupts high-voltage reset threshold hysteresis v hvron v hvrh 27 ? 30 1.5 33 ? v low-voltage reset threshold hysteresis v lvron v lvrh 3.6 ? 4.0 100 4.7 ? v mv high-voltage interrupt threshold hysteresis v hvion v hvih 17.5 ? 21 1.0 23 ? v low-voltage interrupt threshold hysteresis v lvion v lvih 6.5 ? ? 0.4 8.0 ? v high-temperature reset (note 12) threshold hysteresis t ron t rh ? 5.0 170 ? ? ? c high-temperature interrupt (note 13) threshold hysteresis t ion t ih ? 5.0 160 ? ? ? c voltage regulator normal mode output voltage i out = 60 ma, 6.0 v < v sup < 18 v v ddrun 4.75 5.0 5.25 v load regulation i out = 80 ma, v sup = 9.0 v v lr ? ? 100 mv notes 12. this parameter is guaranteed by process monitoring but is not production tested. 13. high-temperature interrupt (hti) threshold is linked to high-temperature reset (htr) threshold (htr = hti + 10 c). static electrical charac teristics (continued) all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 135 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 8 lin physical layer output low level txd low, 500 ? pullup to v sup v lin-low ??1.4 v output high level txd high, i out = 1.0 a v lin-high v sup -1.0 ? ? v pullup resistor to v sup r slave 20 30 60 k ? leakage current to gnd recessive state (-0.5 v < v lin < v sup ) i bus_pas_ rec 0?20 a leakage current to gnd (v sup disconnected) including internal pullup resistor, v lin @ -18 v including internal pullup resistor, v lin @ +18 v i bus_no_gnd i bus ? ? -600 25 ? ? a lin receiver recessive dominant threshold input hysteresis v ih v il v ith v ihy 0.6 v lin 0 ? 0.01 v sup ? ? v sup /2 ? v sup 0.4 v lin ? 0.1 v sup v static electrical charac teristics (continued) all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 135 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 9 half-bridge outputs (h1:h4) switch on resistance @ t j = 25 c with i load = 1.0 a high side low side r ds(on)hb_hs r ds(on)hb_ls ? ? 425 400 500 500 m ? high-side overcurrent shutdown i hbhsoc 3.0 ? 7.5 a low-side overcurrent shutdown i hblsoc 3.0 ? 7.5 a low-side current limitation @ t j = 25 c current limit 1 (cls2 = 0, cls1 = 1, cls0 = 1) current limit 2 (cls2 = 1, cls1 = 0, cls0 = 0) current limit 3 (cls2 = 1, cls1 = 0, cls0 = 1) current limit 4 (cls2 = 1, cls1 = 1, cls0 = 0) current limit 5 (cls2 = 1, cls1 = 1, cls0 = 1) i cl1 i cl2 i cl3 i cl4 i cl5 ? 210 300 450 600 55 260 370 550 740 ? 315 440 650 880 ma half-bridge output high threshold for bemf detection v bemfh ?-300v half-bridge output low threshold for bemf detection v bemfl ?-60-5.0mv hysteresis for bemf detection v bemfhy ?30?mv low-side current-to-voltage ratio (v adout [v]/i hb [a]) csa = 1 csa = 0 ratio h ratio l 7.0 1.0 12.0 2.0 14.0 3.0 v/a switchable v dd output (hvdd) overcurrent shutdown threshold i hvddoct 24 30 40 ma v sup down-scaler voltage ratio (ratio vsup = v sup /v adout )ratio vsup 4.8 5.1 5.35 ? internal die temperature sensor voltage/temperature slope s t to v ?19?mv/c output voltage @ 25c v t25 1.7 2.1 2.5 v static electrical charac teristics (continued) all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 135 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 10 dynamic electrical characteristics all characteristics are for the analog chip only. please refer to the 68hc908ey16 datasheet for ch aracteristics of the microcon troller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 135 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit lin physical layer propagation delay (note 14) , (note 15) txd low to lin low txd high to lin high lin low to rxd low lin high to rxd high txd symmetry rxd symmetry t txd-lin- low t txd-lin- high t lin-rxd- low t lin-rxd- high t txd-sym t rxd-sym ? ? ? ? -2.0 -2.0 ? ? 4.0 4.0 ? ? 6.0 6.0 8.0 8.0 2.0 2.0 s output falling edge slew rate (note 14) , (note 16) 80% to 20% sr f -1.0 -2.0 -3.0 v/ s output rising edge slew rate (note 14) , (note 16) 20% to 80%, r bus > 1.0 k ? , c bus < 10 nf sr r 1.0 2.0 3.0 v/ s lin rise/fall slew rate symmetry (note 14) , (note 16) sr s -2.0 ? 2.0 s autonomous watchdog (awd) awd oscillator period t osc ?40? s awd period low = 512 t osc t awdph 16 22 28 ms awd period high = 256 t osc t awdpl 8.0 11 14 ms notes 14. all lin characteristics are for initial lin sl ew rate selection (20 kbaud) (srs0:srs1= 00). 15. see figure 2 , page 12. 16. see figure 3 , page 12. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 11 . microcontroller for a detailed microcontroller description, refer to the mc68hc908ey16 datasheet. module description core high-performance hc08 core with a ma ximum internal bus frequency of 8.0 mhz timer two 16-bit timers with two channels (tim a and tim b) flash 16 k bytes ram 512 bytes adc 10-bit analog-to-digital converter spi spi module esci standard serial communication interface (sci) module bit-time measurement arbitration prescaler with fine baud-rate adjustment icg internal clock generation module bemf counter special counter for smartmos bemf output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 12 timing diagrams figure 2. lin timing description figure 3. lin slew rate description tx rx lin recessive state recessive state dominant state 0.9 vsup 0.4 vsup 0.6 vsup 0.1 vsup t tx-lin-low t tx-lin-high t lin-rx-low t lin-rx-high t txd-lin-low t txd-lin-high txd rxd 0.4 v sup txd lin 0.9 v sup 0.1 v sup 0.6 v sup t lin-rxd-high t lin-rxd-low sr f = dominant state 0.8 vsup 0.2 vsup 0.8 vsup 0.2 vsup ? t fall-time ? t rise-time ? v fall ? v rise ? v fall ? t fall-time sr r = ? v rise ? t rise-time 0.8 v sup 0.2 v sup 0.2 v sup 0.8 v sup f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 13 functional diagrams figure 4. free wheel diode forward voltage figure 5. dropout voltage on hvdd 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 amperes volts h-bridge low side t j = 25c amperes volts 0 50 100 150 200 250 0 5 10 15 20 25 i load (ma) drop out (mv) t a = 125c t a = 25c t a = -40c dropout (mv) i load (ma) 5.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 14 system/application information introduction the 908e626 device was designed and developed as a highly integrated and cost-effec tive solution for automotive and industrial applications. for automotive body electronics, the 908e626 is well suited to perform stepper motor control, e.g. for climate or light-levelling control via a 3-wire lin bus. this device combines an standard hc08 mcu core (68hc908ey16) with flash memory together with a smartmos ic chip. the smartmos ic chip combines power and control in one chip. power switches are provided on the smartmos ic configured as four half-bridge outputs. other ports are also provided including a selectable hvdd terminal. an internal voltage regulator is provided on the smartmos ic chip, which provides power to the mcu chip. also included in this device is a lin physical layer, which communicates using a single wire. this enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. functional terminal description see figure 1, 908e626 simplified internal block diagram , page 2, for a graphic representation of the various terminals referred to in the following paragraphs. also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. port a i/o terminals these terminals are special-function, bidirectional i/o port terminals that are shared with other functional modules in the mcu. pta0:pta4 are shared with the keyboard interrupt terminals, kbd0:kbd4. the pta5/spsck terminal is not accessible in this device and is internally connected to the spi clock terminal of the analog die. the pta6/ ss terminal is likewise not accessible. for details refer to the 68hc908ey16 datasheet. port b i/o terminals these terminals are special-function, bidirectional i/o port terminals that are shared with other functional modules in the mcu. all terminals are shar ed with the adc module. the ptb6:ptb7 terminals are also shared with the timer b module. ptb0/ad0 is internally connected to the adout terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, v sup , etc. the ptb2/ad2 terminal is not accessible in this device. for details refer to the 68hc908ey16 datasheet. port c i/o terminals these terminals are special-function, bidirectional i/o port terminals that are shared with other functional modules in the mcu. for example, ptc2:ptc4 are shared with the icg module. ptc0/miso and ptc1/mosi are not accessible in this device and are internally connect ed to the miso and mosi spi terminals of the analog die. for details refer to the 68hc908ey16 datasheet. port d i/o terminals ptd1/tach1 and ptd0/tach0/bemf are special- function, bidirectional i/o port terminals that can also be programmed to be timer terminals. in step motor applications the ptd0 terminal should be connected to the bemf output of the analog die in order to evaluate the bemf signal with a special bemf module of the mcu. ptd1 terminal is recommended for use as an output terminal for generating the fgen signal (pwm signal) if required by the application. port e i/o terminal pte1/rxd and pte0/txd are special-function, bidirectional i/o port terminals that can also be programmed to be enhanced serial communication. pte0/txd is internally connected to the txd terminal of the analog die. the connection for the receiver must be done externally. external interrupt terminal ( irq ) the irq terminal is an asynchronous external interrupt terminal. this terminal contains an internal pullup resistor that is always activated, even when the irq terminal is pulled low. for details refer to the 68hc908ey16 datasheet. external reset terminal ( rst ) a logic [0] on the rst terminal forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when an y internal reset source is asserted. this terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled low. for details refer to the 68hc908ey16 datasheet. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 15 current limitation frequency input terminal (fgen) input terminal for the half-bridge current limitation pwm frequency. this input is not a r eal pwm input terminal; it should just supply the period of th e pwm. the duty cycle will be generated automatically. important the recommended fgen frequency should be in the range of 0.1 khz to 20 khz. back electromagnetic force output terminal (bemf) this terminal gives the user information about back electromagnetic force (bemf). this feature allows stall detection and coil failures in st ep motor applications. in order to evaluate this signal the terminal must be directly connected to terminal ptd0/tach0/bemf. reset terminal ( rst_a ) rst_a is the bidirectional reset terminal of the analog die. it is an open drain with pullup resi stor and must be connected to the rst terminal of the mcu. interrupt terminal ( irq_a ) irq_a is the interrupt output terminal of the analog die indicating errors or wake-up events. it is an open drain with pullup resistor and must be connected to the irq terminal of the mcu. slave select terminal ( ss ) this terminal is the spi slave select terminal for the analog chip. all other spi connections are done internally. ss must be connected to ptb1 or any other logic i/o of the microcontroller. lin bus terminal (lin) the lin terminal represents the single-wire bus transmitter and receiver. it is suited fo r automotive bus systems and is based on the lin bus specification. half-bridge output terminals (hb1:hb4) the 908e626 device includes power mosfets configured as four half-bridge driver outputs. the hb1:hb4 outputs may be configured for step motor driver s, dc motor drivers, or as high-side and low-side switches. the hb1:hb4 outputs are short- circuit and overtemperature protected, and they fe ature current recopy, current limitation, and bemf generation. current limitation and recopy are done on the low-side mosfets. power supply terminals (vsup1:vsup3) vsup1:vsup3 are device power supply terminals. the nominal input voltage is designed for operation from 12 v systems. owing to the low on-resistance and current requirements of the half-bridge dr iver outputs, multiple vsup terminals are provided. all vsup terminals must be connected to get full chip functionality. power ground terminals (gnd1 and gnd2) gnd1 and gnd2 are device power ground connections. owing to the low on-resistance and current requirements of the half-bridge driver outputs multiple terminals are provided. gnd1 and gnd2 terminals must be connected to get full chip functionality. switchable v dd output terminal (hvdd) the hvdd terminal is a switchable v dd output for driving resistive loads requiring a regulat ed 5.0 v supply; the output is short-circuit protected. +5.0 v voltage regulator output terminal (vdd) the vdd terminal is needed to place an external capacitor to stabilize the regulated output voltage. the vdd terminal is intended to supply the embedded microcontroller. important the vdd terminal should not be used to supply other loads; use the hvdd terminal for this purpose. the vdd, evdd, vdda, and vrefh terminals must be connected together. voltage regulator ground terminal (vss) the vss terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). important vss, evss, vssa, and vr efl terminals must be connected together. lin transceiver output terminal (rxd) this terminal is the output of lin transceiver. the terminal must be connected to the microcontroller?s enhanced serial communications interface (esc i) module (rxd terminal). adc reference terminals (vrefl and vrefh) vrefl and vrefh are the reference voltage terminals for the adc. it is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. important vrefh is the high reference supply for the adc and should be tied to the same potential as vdda via separate traces. vrefl is the low reference supply for the adc and should be tied to the same pot ential as vss via separate traces. for details refer to the 68hc908ey16 datasheet. adc supply terminals (vdda and vssa) vdda and vssa are the power supply terminals for the analog-to-digital converter (adc) . it is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 16 important vdda is the supply for the adc and should be tied to the same potential as evdd via separate traces. vssa is the ground terminal for the adc and should be tied to the same potential as evss vi a separate traces. for details refer to the 68hc908ey16 datasheet. mcu power supply terminals (evdd and evss) evdd and evss are the power supply and ground terminals. the mcu operates from a single power supply. fast signal transitions on mcu terminals place high, short- duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu. for details refer to the 68hc908ey16 datasheet. test terminal (flsvpp) for test purposes only. do not connect in the application. exposed pad terminal the exposed pad terminal on the bottom side of the package conducts heat from the chip to the pcb board. for thermal performance the pad must be soldered to the pcb board. it is recommended that the pad be connected to the ground potential. analog die description interrupts the 908e626 has five different interrupt sources as described in the following paragraphs. the interrupts can be disabled or enabled via the spi. after reset all interrupts are automatically disabled. low-voltage interrupt the low-voltage interrupt (lvi) is related to the external supply voltage, v sup . if this voltage falls below the lvi threshold, it will set the lvi flag. if the low-voltage interrupt is enabled, an interrupt will be initiated. with lvi the h-bridges (high-side mosfet only) are switched off. all other modules are not influenced by this interrupt. high-voltage interrupt the high-voltage interrupt (hvi) is related to the external supply voltage, v sup . if this voltage rises above the hvi threshold, it will set the hvi flag. if the high-voltage interrupt is enabled, an interrupt will be initiated. with hvi the h-bridges (high-side mosfet only) are switched off. all other modules are not influenced by this interrupt. high-temperature interrupt the high-temperature interrupt (hti) is generated by the on-chip temperature s ensors. if the chip temperature is above the hti threshold, the hti flag will be set. if the high- temperature interrupt is enabled, an interrupt will be initiated. lin interrupt if the linie bit is set, a falling edge on the lin terminal will generate an interrupt. overcurrent interrupt if an overcurrent condition on a half-bridge or the hvdd output is detected and the ocie bit is set and an interrupt generated. interrupt flag register (ifr) linf ? lin flag bit this read/write flag is set on the falling edge at the lin data line. clear linf by writing a logic [1] to linf. reset clears the linf bit. writing a logic [0] to linf has no effect. ? 1 = falling edge on lin data line has occurred. ? 0 = falling edge on lin data line has not occurred since last clear. htf ? high-temperature flag bit this read/write flag is set on a high-temperature condition. clear htf by writing a logic [1] to htf. if a high-temperature condition is still present while writing a logic [1] to htf, the writing has no effect. therefor e, a high-temperature interrupt cannot be lost due to inadvertent clearing of htf. reset clears the htf bit. writing a logic [0] to htf has no effect. ? 1 = high-temperature condition has occurred. ? 0 = high-temperature condition has not occurred. register name and address: ifr - $05 bit7 6 5 4 3 2 1 bit0 read 0 0 linf htf lvf hvf ocf 0 write reset 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 17 lvf ? low-voltage flag bit this read/write flag is set on a low-voltage condition. clear lvf by writing a logic [1] to lvf. if a low-voltage condition is still present while writing a logic [1] to lvf, the writing has no effect. therefore, a low-voltage inte rrupt cannot be lost due to inadvertent clearing of lvf. rese t clears the lvf bit. writing a logic [0] to lvf has no effect. ? 1 = low-voltage condition has occurred. ? 0 = low-voltage condition has not occurred. hvf ? high-voltage flag bit this read/write flag is set on a high-voltage condition. clear hvf by writing a logic [1] to hvf. if high-voltage condition is still present while writing a logic [1] to hvf, the writing has no effect. therefore, a high-voltage interru pt cannot be lost due to inadvertent clearing of hvf. reset clears the hvf bit. writing a logic [0] to hvf has no effect. ? 1 = high-voltage condition has occurred. ? 0 = high-voltage condition has not occurred. ocf ? overcurrent flag bit this read-only flag is set on an overcurrent condition. reset clears the ocf bit. to clear this flag, write a logic [1] to the appropriate overcurrent flag in the sysstat register. see figure 6 , which shows the two signals triggering the ocf. ? 1 = high-current condition has occurred. ? 0 = high-current condition has not occurred. figure 6. principal implementation for ocf interrupt mask register (imr) linie ? lin line interrupt enable bit this read/write bit enables cpu interrupts by the lin flag, linf. reset clears the linie bit. ? 1 = interrupt requests from linf flag enabled. ? 0 = interrupt requests from linf flag disabled. htie ? high-temperature in terrupt enable bit this read/ write bit enables cpu interrupts by the high- temperature flag, htf. re set clears the htie bit. ? 1 = interrupt requests from htf flag enabled. ? 0 = interrupt requests from htf flag disabled. lvie ? low-voltage interrupt enable bit this read/write bit enables cpu interrupts by the low- voltage flag, lvf. rese t clears the lvie bit. ? 1 = interrupt requests from lvf flag enabled. ? 0 = interrupt requests from lvf flag disabled. hvie ? high-voltage inte rrupt enable bit this read/write bit enables cpu interrupts by the high- voltage flag, hvf. reset clears the hvie bit. ? 1 = interrupt requests from hvf flag enabled. ? 0 = interrupt requests from hvf flag disabled. ocie ? overcurrent interr upt enable bit this read/write bit enables cpu interrupts by the overcurrent flag, ocf. reset clears the ocie bit. ? 1 = interrupt requests from ocf flag enabled. ? 0 = interrupt requests from ocf flag disabled. ocf hvdd_ocf hb_ocf register name and address: imr - $04 bit7 6 5 4 3 2 1 bit0 read 0 0 linie htie lvie hvie ocie 0 write reset 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 18 reset the 908e626 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. figure 7 depicts the internal reset sources. figure 7. internal reset routing reset internal sources autonomous watchdog awd modules generates a reset because of a timeout (watchdog function). high-temperature reset to prevent damage to the devic e, a reset will be initiated if the temperature rises above a certain value. the reset is maskable with bit htre in the reset mask register. after a reset the high-temperature reset is disabled. low-voltage reset the lvr is related to the internal v dd . in case the voltage falls below a certain threshold, it will pull down the rst_a terminal. high-voltage reset the hvr is related to the external v sup voltage. in case the voltage is above a certain threshold, it will pull down the rst_a terminal. the reset is maskable with bit hvre in the reset mask register. after a reset the high-voltage reset is disabled. reset external source external reset terminal the microcontroller has the capability of resetting the smartmos device by pulling down the rst terminal. reset mask register (rmr) ttest ? high-temperatu re reset test this read/write bit is for test purposes only. it decreases the overtemperature shutdown limit for final test. reset clears the htre bit. ? 1 = low-temperature threshold enabled. ? 0 = low-temperature threshold disabled. htre flag hvre flag awdre flag awd reset sensor high-voltage reset sensor high-temperature reset sensor mono flop low-voltage reset vdd rst_a spi registers register name and address: rmr - $06 bit7 6 5 4 3 2 1 bit0 read ttest 0 0 0 0 0 hvre htre write reset 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 19 hvre ? high-voltage re set enable bit this read/write bit enables resets on high-voltage conditions. reset clears the hvre bit. 1 = high-voltage reset enabled. 0 = high-voltage reset disabled. htre ? high-temperature reset enable bit this read/write bit enables resets on high-temperature conditions. reset clears the htre bit. ? 1 = high-temperature reset enabled. ? 0 = high-temperature reset disabled. serial peripheral interface the serial peripheral interface (spi) creates the communication link between the microcontroller and the 908e626. the interface consists of four terminals (see figure 8 ): ? ss ?slave select ? mosi?master-out slave-in ? miso?master-in slave-out ? spsck?serial clock (maximum frequency 4.0 mhz) a complete data transfer via t he spi consists of 2 bytes. the master sends address and data, slave system status, and data of the selected address. figure 8. spi protocol during the inactive phase of ss , the new data transfer is prepared. the falling edge on the ss line indicates the start of a new data transfer and puts mi so in the low-impedance mode. the first valid data are moved to miso with the rising edge of spsck. the miso output changes data on a rising edge of spsck. the mosi input is sampled on a falling edge of spsck. the data transfer is only valid if exactly 16 sample clock edges are present in the active phase of ss . after a write operation, the tran smitted data is latched into the register by the rising edge of ss . register read data is internally latched into the spi at the time when the parity bit is transferred. ss high forces miso to high impedance. s7 s6 s5 s4 s3 s2 s1 s0 r/w a4 a3 a2 a1 a0 p x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 system status register read/write, address, parity data (register write) data (register read) rising edge of spsck change miso/mosi output falling edge of spsck sample miso/mosi input slave latch register address slave latch data ss mosi miso spsck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 20 master address byte a4:a0 contains the address of the desired register. r/ w contains information about a read or a write operation. ?if r/ w = 1, the second byte of master contains no valid information, slave just tran smits back register data. ?if r/ w = 0, the master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to wr ite operation, write data is latched in the smartmos register on rising edge of ss . parity p the parity bit is equal to ?0? if the number of 1 bits is an even number contained within r/ w , a4:a0. if the number of 1 bits is odd, p equals ?1?. for example, if r/ w = 1, a4:a0 = 00001, then p equals ?0.? the parity bit is only evaluated during a write operation. bit x not used. master data byte contains data to be written or no valid data during a read operation. slave status byte contains the contents of the s ystem status register ($0c) independent of whether it is a wr ite or read operation or which register was selected. slave data byte contains the contents of sele cted register. during a write operation it includes the regi ster content prior to a write operation. spi register overview table 1 summarizes the spi register addresses and the bit names of each register. table 1. list of registers addr register name r/w bit 7 6543210 $01 h-bridge output (hbout) r hb4_h hb4_l hb3_h hb3_l hb2_h hb2_l hb1_h hb1_l w $02 h-bridge control (hbctl) r ofc_en csa 000 cls2 cls1 cls0 w $03 system control (sysctl) r pson srs1 srs0 0000 0 w $04 interrupt mask (imr) r 0 0 liniehtie lvie hvieocie 0 w $05 interrupt flag (ifr) r 0 0 linf htf lvf hvf ocf 0 w $06 reset mask (rmr) r ttest 00000 hvre htre w $07 analog multiplexer configuration (admux) r0 000 ss3 ss2 ss1 ss0 w $08 reserved r0 0000 000 w $09 reserved r0 0000000 w $0a awd control (awdctl) r0 0 0 awdre 0 0 awdf awdr w awdrst $0b power output (pout) r0 0 0 0 0 0 hvddon 0 w $0c system status (sysstat) r 0 lincl hvdd_ocf 0 lvf hvf hb_ocf htf w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 21 analog die i/os lin physical layer the lin bus terminal provides a physical layer for single-wire communication in automotive applications. the lin physical layer is designed to meet the lin physical layer specification. the lin driver is a low-side mosfet with internal current limitation and thermal shutdown. an internal pullup resistor with a serial diode structure is in tegrated, so no external pullup components are required for the application in a slave node. the fall time from dominant to recessive and the rise time from recessive to dominant is controlled. the symmetry between both slew rate controls is guaranteed. the lin terminal offers high susceptibility immunity level from external disturbance, gu aranteeing communication during external disturbance. the lin transmitter circuitry is enabled by setting the pson bit in the system control regist er (sysctl). if the transmitter works in the current limitation region, the lincl bit in the system status register (sysstat ) is set. due to excessive power dissipation in the transmit ter, software is advised to monitor this bit and turn the transmitter off immediately. txd terminal the txd terminal is the mcu interface to control the state of the lin transmitter (see figure 1 , page 2). when txd is low, lin output is low (dominant st ate). when txd is high, the lin output mosfet is tur ned off. the txd terminal has an internal pullup current source in order to set the lin bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. rxd terminal the rxd transceiver terminal is the mcu interface, which reports the state of the lin bu s voltage. lin high (recessive state) is reported by a high le vel on rxd, lin low (dominant state) by a low level on rxd. analog multiplexe r/adout terminal the adout terminal is the analog output interface to the adc of the mcu (see figure 1 , page 2). an analog multiplexer is used to read six internal diagnostic analog voltages. current recopy the analog multiplexer is connected to the four low-side current sense circuits of the ha lf-bridges. these sense circuits offer a voltage proportional to the current through the low-side mosfet. high or low resolution is selectable: 5.0 v/2.5 a or 5.0 v/500 ma, respectively. (refer to half-bridge current recopy on page 25 .) temperature sensor the 908e626 includes an on-chip temperature sensor. this sensor offers a voltage that is proportional to the actual chip junction temperature. v sup prescaler the v sup prescaler permits the r eading or measurement of the external supply voltage. t he output of this voltage is v sup / ratio vsup . the different internal diagnostic analog voltages can be selected with the admux register. analog multiplexer configur ation register (admux) ss3, ss2, ss1, and ss0?a/d input select bits these read/write bits select the input to the adc in the microcontroller according to table 2 , page 22. reset clears ss3, ss2, ss1, and ss0 bits. register name and address: admux - $07 bit7 6 5 4 3 2 1 bit0 read 0 0 0 0 ss3 ss2 ss1 ss0 write reset 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 22 table 2. analog multiplexer configuration register power output register (pout) hvddon?hvdd on bit this read/write bit enables hvdd output. reset clears the hvddon bit. ? 1 = hvdd enabled. ? 0 = hvdd disabled. half-bridges outputs hb1:hb4 provide four low-resistive half-bridge output stages. the half-bridges can be used in h-bridge, high- side, or low-side configurations. reset clears all bits in the h-bridge output register (hbout) owing to the fact that all half-bridge outputs are switched off. hb1:hb4 output features: ? short circuit (overcurrent) protection on high-side and low- side mosfets. ? current recopy feat ure (low side mosfet). ? overtemperature protection. ? overvoltage and undervoltage protection. ? current limitation feature (low side mosfet). ss3 ss2 ss1 ss0 channel 0 0 0 0 current recopy hb1 0 0 0 1 current recopy hb2 0 0 1 0 current recopy hb3 0 0 1 1 current recopy hb4 0 1 0 0 v sup prescaler 0 1 0 1 temperature sensor 0 1 1 0 not used 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 register name and address: p out - $0b bit7 6 5 4 3 2 1 bit0 read 0 0 0 (note 17) 0 (note 17) 0 (note 17) 0 (note 17) hvddon 0 (note 17) write reset 0 0 0 0 0 0 0 0 notes 17. this bit must always be set to 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 23 figure 9. half-bridge push-pull output driver half-bridge control each output mosfet can be controlled individually. the general enable of the circuitry is done by setting pson in the system control register (sysctl). hbx_l and hbx_h form one half-bridge. it is not possible to switch on both mosfets in one half-bridge at the same time. if both bits are set, the high- side mosfet has a higher priority. to avoid both mosfets (high side and low side) of one half- bridge being on at the same time, a break-before-make circuit exists. switching the high-side mosfet on is inhibited as long as the potential between gate and v ss is not below a certain threshold. switching the low-side mosfet on is blocked as long as the potential between gate and source of the high-side mosfet did not fall below a certain threshold. half-bridge output register (hbout) hbx_l?low-side on/off bits these read/write bits turn on the low-side mosfets. reset clears the hbx_l bits. ? 1 = low-side mosfet turned on for half-bridge output x. ? 0 = low-side mosfet turned off for half-bridge output x. hbx_h?high-side on/off bits these read/write bits turn on the high-side mosfets. reset clears the hbx_h bits. 1 = high-side mosfet turned on for half-bridge output x. 0 = high-side mosfet turned on for half-bridge output x. high-side driver charge pump, overtemperature protection, overcurrent protection low-side driver current recopy, current limitation, overcurrent protection control on/off status on/off status current limit hbx vsup gnd bemf register name and address: hbout - $01 bit7 6 5 4 3 2 1 bit0 read hb4 _ h hb4 _ l hb3 _ h hb3 _ l hb2 _ h hb2 _ l hb1 _ h hb1 _ l write reset 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 24 half-bridge current limitation each low-side mosfet offers a current limit or constant current feature. this features is realized by a pulse width modulation on the low-side mosfet. the pulse width modulation on the outputs is cont rolled by the fgen input and the load characteristics. the fgen input provides the pwm frequency, whereas the duty cycle is controlled by the load characteristics. the recommended frequency range for the fgen and the pwm is 0.1 khz to 20 khz. functionality each low-side mosfet switches off if a current above the selected current limit was detected. the 908e626 offers five different current limits (refer to table 3 , page 27, for current limit values). the low-side mosfet switches on again if a rising edge on the fgen input was detected ( figure 10 ). figure 10. half-bri dge current limitation coil current half-bridge low-side output fgen input (mcu pwm signal) minimum 50 s h-bridge low-side mosfet will be switched off if select current limit is reached. h-bridge low-side mosfet will be turned on with each rising edge of the fgen input. t (s) t (s) t (s) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 25 offset chopping if bit ofc_en in the h-bridge control register (hbctl) is set, hb1 and hb2 will continue to switch on the low-side mosfets with the rising edge of the fgen signal and hb3 and hb4 will switch on the low-side mosfets with the falling edge on the fgen input. in step motor applications, this feature allows the reduction of emi due to a reduction of the di/dt ( figure ). figure 11. offset chopping for step motor control half-bridge current recopy each low-side mosfet has an additional sense output to allow a current recopy feature. th is sense source is internally connected to a shunt resistor. t he drop voltage is amplified and switched to the analog multiplexer. the factor for the current sens e amplification can be selected via bit csa in the system control register. ? csa = 1: low resolution selected (500 ma measurement range). ? csa = 0: high resolution selected (2.5 a measurement range). half-bridge bemf generation the bemf output is set to ?1? if a recirculation current is detected in any half-bridge. this recirculation current flows via the two freewheeling diodes of the power mosfets. the bemf circuitry detects that and generates a high on the bemf output as long as a recirculation current is detected. this signal provides a flexible and reliable detection of stall in step motor applications. for this the bemf circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. in addition the signal can be used for open load detection (absence of this signal) (see figure 12 , page 26). coil2 current coil1 current current in vsup line fgen input (mcu pwm signal) coil1 ?.. coil2 ?.. hb1 hb2 hb3 hb4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 26 figure 12. bemf signal generation half-bridge overtemperature protection the half-bridge outputs prov ide an overtemperature pre- warning with the htf in the inte rrupt flag register (ifr). in order to protect the outputs against overte mperature, the high- temperature reset must be enabled. if this value is reached, the part generates a reset and disables all power outputs. half-bridge overcurrent protection the half-bridges are protected against short to gnd, short to vsup, and load shorts. in the event an overcurrent on the high side is detected, the high-side mosfets on all hb high-side mosfets are switched off automatically. in the event an overcurrent on the low side is detected, all hb lo w-side mosfets are switched off automatically. in both cases, the overcurrent status flag hb_ocf in the system status register (sysstat) is set. the overcurrent status flag is cleared (and the outputs re- enabled) by writing a logic [1] to the hb_ocf flag in the system status register or by reset. half-bridge overvoltage/undervoltage the half-bridge outputs are pr otected against undervoltage and overvoltage conditions. this protection is done by the low- and high-voltage interrupt circuitry. if one of these flags (lvf, hvf) is set, the outputs are automatically disabled. the overvoltage/undervoltage st atus flags are cleared (and the outputs re-enabled) by writ ing a logic [1] to the lvf/hvf flags in the interrupt flag register or by reset. clearing this flag is useless as long as a high- or low-voltage condition is present. half-bridge contro l register (hbctl) ofc_en?h-bridge offset chopping enable bit this read/write bit enables offset chopping. reset clears the ofc_en bit. ? 1 = offset chopping enabled. ? 0 = offset chopping disabled. csa?h-bridges current sense amplification select bit this read/write bit selects the current sense amplification of the h-bridges. reset clears the csa bit. ? 1 = current sense amplification set for measuring 0.5 a. ? 0 = current sense amplification set for measuring 2.5 a. coil current voltage on 1 1 bemf signal register name and address: hbctl - $02 bit7 6 5 4 3 2 1 bit0 read ofc_en csa 0 0 0 cls2 cls1 cls0 write reset 0 0 0 0 0 0 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 27 cls2:cls0?h-bridge current limitation selection bits these read/write bits select the current limitation value according to table 3 . reset clears the cls2:cls0 bits. table 3. h-bridge current limitation value selection bits switchable vdd outputs the hvdd terminal is a switchable vdd output terminal. it can be used for driving external circuitry that requires a v dd voltage. the output is enabled with bit pson in the system control register and can be switched on/off with bit hvddon in the power output register. lo w- or high-voltage conditions (lvi/hvi) have no influence on this circuitry. hvdd overtemperature protection overtemperature protection is enabled if the high- temperature reset is enabled. hvdd overcurrent protection the hvdd output is protected against overcurrent. in the event the overcurrent limit is or was reached, the output automatically switches off and th e hvdd overcurrent flag in the system status register is set. system control register (sysctl) pson?power stages on bit this read/write bit enables the power stages (half-bridges, lin transmitter and hvdd output). reset clears the pson bit. ? 1 = power stages enabled. ? 0 = power stages disabled. srs0:srs1?lin slew rate selection bits these read/write bits enable the user to select the appropriate lin slew rate for di fferent baud rate configurations as shown in table 4 . the high speed slew rates are used, for example, for programming via the lin and are not intended for use in the application. table 4. lin slew rate selection bits system status register (sysstat) lincl ? lin current limitation bit this read-only bit is set if t he lin transmitter operates in current limitation region. due to excessive power dissipation in the transmitter, software is advi sed to turn the transmitter off immediately. ? 1 = transmitter operating in current limitation region. ? 0 = transmitter not operating in current limitation region. hvdd_ocf?hvdd output overcurrent flag bit this read/write flag is set on an overcurrent condition at the hvdd terminal. clear hvdd_ocf and enable the output by writing a logic [1] to the hvdd_ocf flag. reset clears the hvdd_ocf bit. writing a logic [0] to hvdd_ocf has no effect. ? 1 = overcurrent condition on hvdd has occurred. ? 0 = no overcurrent condition on hvdd has occurred. lvf?low-voltage bit this read only bit is a copy of the lvf bit in the interrupt flag register. ? 1 = low-voltage condition has occurred. ? 0 = no low-voltage condition has occurred. hvf? high-voltage sensor bit this read-only bit is a copy of the hvf bit in the interrupt flag register. ? 1 = high-voltage condition has occurred. ? 0 = no high-voltage condition has occurred. cls2 cls1 cls0 current limit 0 0 0 no limit 0 0 1 0 1 0 0 1 1 55 ma (typ) 1 0 0 260 ma (typ) 1 0 1 370 ma (typ) 1 1 0 550 ma (typ) 1 1 1 740 ma (typ) register name and address: sysctl - $03 bit7 6 5 4 3 2 1 bit0 read pson srs1 srs0 0 0 0 0 0 (note 17) write reset 0 0 0 0000 0 notes 18. this bit must always be set to 0. srs1 srs0 lin slew rate 0 0 initial slew rate (20 kbaud) 0 1 slow slew rate (10 kbaud) 1 0 high speed ii (8x) 1 1 high speed i (4x) register name and address: sysstat - $0c bit7 6 5 4 3 2 1 bit0 read 0 lincl hvdd _ocf 0 lvf hvf hb_ ocf htf write reset 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 28 hb_ocf?h-bridge over current flag bit this read / write flag is set on an overcurrent condition at the h-bridges. clear hb_ocf and enable the h-bridge driver by writing a logic [1] to hb_ocf. reset clears the hb_ocf bit. writing a logic [0] to hb_ocf has no effect. ? 1 = overcurrent condition on h-bridges has occurred. ? 0 = no overcurrent condition on h-bridges has occurred. htf?overtemperature status bit this read-only bit is a copy of the htf bit in the interrupt flag register. ? 1 = overtemperature condition has occurred. ? 0 = no overtemperature condition has occurred. autonomous watchdog (awd) the autonomous watchdog module allows to protect the cpu against code runaways. the awd is enabled if awdre in the awdctl register is set. if this bit is cleared, the awd oscillator is disabled and the watchdog switched off. watchdog the watchdog function is only available in run mode. on setting the awdre bit, watchdog functionality in run mode is activated. once this function is enabled, it is not possible to disable it via software. if the timer reache s end value and awdre is set, a system reset is initiated. operations of t he watchdog function cease in stop mode. normal operation will be continued when the system is back to run mode. to prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. this is done by a write to the awdrst bit in the awdctl register. autonomous watchdog control register (awdctl) awdrst?autonomous wa tchdog reset bit this write-only bit resets th e autonomous watchdog timeout period. awdrst always reads 0. reset clears awdrst bit. ? 1 = reset awd and restart timeout period. ? 0 = no effect. awdre?autonomous watchdog reset enable bit this read/write bit enables resets on awd timeouts. a reset on the rst_a is asserted when the autonomous watchdog has reached the timeout and the autonomous watchdog is enabled. awdre is one-time setable (write once) after each reset. reset clears the awdre bit. ? 1 = autonomous watchdog enabled. ? 0 = autonomous watchdog disabled. awdr?autonomous watchdog rate bit this read/write bit selects the clock rate of the autonomous watchdog. reset clears the awdr bit. ? 1 = fast rate selected (10 ms). ? 0 = slow rate selected (20 ms). voltage regulator the 908e626 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the mcu. the v dd regulator accepts a unregulated input supply and provides a regulated v dd supply to all digital sections of the device. the output of the regulator is also connected to the vdd terminal to provide the 5.0 v to the microcontroller. register name and address: awdctl - $0a bit7 6 5 4 3 2 1 bit0 read 00 0 awdre 0 (note 17) 0 (note 17) 0 awdr write awdrst reset 00 0 0 0 0 0 0 notes 19. this bit must always be set to 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 29 factory trimming and calibration to enhance the ease-of-use of the 908e626, various parameters (e.g. icg trim value) are stored in the flash memory of the device. the following flash memory locations are reserved for this purpose and might have a value different from the ?empty? (0xff) state: ? 0xfd80:0xfddf trim and calibration values ? 0xfffe:0xffff reset vector in the event the application us es these parameters, one has to take care not to erase or override these values. if these parameters are not used, these flash locations can be erased and otherwise used. package thermal performance figure 13 shows a thermal response curve for a package mounted onto a thermally enhanced pcb. note the pcb board is a multi-layer board with two inner copper planes (2s2p). the bo ard conforms to jedec eia/ jesd 51-5 and jesd51-7. subs trate thickness is 1.60 mm. top and bottom copper trace layers are 0.7 mm thick, with two inner copper planes of 0.35 mm thickness. thermal vias have 0.35 mm thick plating. figure 13. thermal response of h-bridge driver with package soldered to a jedec pcb board 0 5 10 15 20 25 30 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 10000 time[s ] thermal impedance [ oc /w] time (s) thermal impedance (c/w) 1.0 5.0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
908e626 motorola analog integrated circuit device data 30 package dimensions notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. datums b and c to be determined at the plane where the bottom of the leads exit the plastic body. this dimension does not include mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.15 mm per side. this dimension is determined at the plane where the bottom of hte leads exit the plastic body. this dimension does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. this dimension does not incude dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.46 mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead shall not be less than 0.07 mm. exact shape of each corner is optional. these dimensions apply to the flat section of the lead between 0.1 mm and 0.3 mm from the lead tip. the package top may be smaller than the package bottom. this dimension is determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and inter-lead flash, but including any mismatch between the top and botom of the plastic body. 17.8 7.4 1 27 28 54 b 9 5 c 7.6 18.0 9 4 10.3 5.15 0.3 a b c 2x 27 tips bb pin 1 index c l 0.10 a 2.35 seating plane 0.65 a 54x 52x 2.65 0.9 section b-b r0.08 min 0.1 0.0 0.5 0 ? 8 ? 0 ? 0.25 gauge plane min (1.43) a a c c (0.29) 0.38 0.30 (0.25) plating base metal section a-a rotated 90? clockwise 8 0.25 0.22 m 0.13 c ab 6 10.9 9.7 0.30 c ab 5.3 4.8 0.30 c ab view c-c dwb suffix 54-terminal soic wide body exposed pad plastic package case 1400-01 issue b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 908e626 31 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
information in this document is provided solely to enable system and software implem enters to use motorola products. there are no express or implied copyright licenses granted hereunder to desig n or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 mm908e626 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

▲Up To Search▲

Price & Availability of MM908E626AVDWBR2

	To Download MM908E626AVDWBR2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .